Memory arrays can use redundant memory elements (i.e., cells and accompanying wordlincs and bitlines organized as rows or columns) to compensate for production errors. Specifically, after the production of a complete memory array, a post production test in the memory array is generally performed. The post-production testing may indicate that a particular column, row or cell of the memory array is defective. A redundant memory element can then be substituted for the defective element(s). This substitution typically occurs after the entire memory array has been manufactured. By allowing a defective memory element to be replaced by a redundant element after production, the memory array can still be used.
One conventional approach to repair column failures in a memory array typically required a fuse for each column to be disabled. FIG. 1 illustrates a circuit 10 for disabling a defective column using a fuse. The circuit 10 generally comprises an address decoder 12, a fuse 14 and a pass gate 16 for each of the columns in the memory array. Each address decoder 12 generally has a fuse 14 at its output. When the fuse 14 is blown, the pass gate 16 is permanently disconnected from the decoder 12. A small pull-down, or pull-up leaker path 18 generally ensures that the pass gate 16 stays shut. The pass gate 16 has inputs 24 and 26 received from the bitlines of the memory column and an output 20 and an output 22 (e.g., local data lines or tbus) that are connected to additional pass gates, a sense amplifier and a write driver. Since each column of the array in this approach may require a fuse 14 to be disconnected, the impact on die area is large. A spare column can be multiplexed into the normal sense amplifier or a combined spare column and sense amplifier may be implemented to replace the faulty column previously disabled.
Often an entire block of columns is replaced even though only a single column exhibits a fault. This generally occurs when a single fuse is used to disable a block of cells which contains two or more columns. While disabling columns in blocks requires less fuses than the first method, the technique is an inefficient use of die area since several spare columns may ultimately be used to repair a single bad column. Additionally, there may be no means to replace a spare block if one of the columns in the spare block also contains a fault.
FIG. 2 illustrates a circuit 30 implementing a block approach to replacing a defective column. Each I/O cell 32 has an associated read/write circuit 34 and a block of main memory 38. One or more spare memory and read/write circuits 36 and memory blocks 40 are provided such that they can be connected to an I/O cell to replace one of the main blocks, should the main block be faulty.
Static random access memories (SRAMs) tend to have memory cell data levels near a supply rail voltage. The bitlines may have pull-up or pull-down devices to help clamp the lines at the supply voltage such that, for example, a logic high is indicated by VCC and a logic low by (VCC-100 mV). The bitlines are often fabricated on the same interconnect layer as the memory core power supply routing. If a bitline is shorted to the opposite supply due to a manufacturing defect, the chip current (ICC) may increase to an undesirable level. It may also no longer be possible to read or write arbitrary data to any memory cell on that column as one bitline will be permanently held by the short despite the efforts of the cell (read) or write driver (write). One of the columns in the memory block is accessed via a bi-directional multiplexer built from column pass gates under control of a column address. The individual column bitline pairs are multiplexed to a common local data line or bus pair which is in turn connected to the block sense amplifier and write driver. A further functional failure may also result due to the shorted bitline charging/discharging the local data line. If the charging/discharging is too great, the subsequent access of a good column may be affected as the data line and hence bitline is no longer initially at a near-supply level. In the worst case, failure to precharge the local data line may result in the memory cell drive current being overcome by the charge on the local data line, thereby undesirably changing the logic state of the cell.
To prevent the extra ICC and/or functional failure, bitlines are often provided with additional fuses to disconnect them from the supply to which they are normally clamped. FIG. 3 shows a typical example of a circuit 50 implementing such a bitline disconnect. The circuit 50 comprises a fuse 52, a column of memory cells connected to complementary bitlines 54 and 56 and bitline pull-ups 58 and 60. Blowing the fuse 52 removes the possibility of a path between VCC and GND via the bitlines. For a block replacement redundancy scheme the circuit 50' is often used to reduce the number of fuses. Here, all the bitlines 72, 74, 72n 74n in the n columns have their pull-ups 80, 82, 80n, 82n commonly connected to the supply by a single fuse 70. The fuse 70 can therefore disable the whole block. Either arrangement consumes die area for the fuses.
In general, it is desirable to maintain a balance between providing sufficient quantity of spare elements as well as flexibility in the implementation of the spare memory elements. Desirable design criteria often include both the ability to repair faulty elements while minimizing the overall die area. In modern memory technologies, (e.g., 0.5 .mu.m gate width or less), the fuse center to fuse center pitch is typically similar or greater than the pitch of a memory column. Thus, the layout of a circuit with a fuse per column typically results in two or more rows of fuses, greatly impacting die area consumed. Circuitry pitched to the memory columns (or rows) is very expensive in terms of die area, compared to circuits in the chip periphery that can be laid out in an arbitrary manner. Therefore, one of ordinary skill in the art also desires to minimize the number of fuses. Additionally, one also wants to keep the overall cost of producing the chip to a minimum.